Blogs (28) >>
ECOOP 2016
Sun 17 - Fri 22 July 2016 Rome, Italy
Tue 19 Jul 2016 14:20 - 14:50 at Belli - Session 3 Chair(s): Davide Ancona

Modern multicore processor architectures and compilers of shared-memory concurrent programming languages provide only weak memory consistency guarantees. A memory model specifies which write action can be seen by a read action between concurrent threads. The most well known memory model is the sequentially consistent (SC) model but, to improve performance, modern architectures and languages employ relaxed memory models where a read may not see the most recent write that has been performed by other threads. These models come in different formalization styles (axiomatic, operational) and have their own advantages and disadvantages.

In a POPL’13 paper, Demange et al [12], proposed an alternative style that is fully characterized in terms of the reorderings it allows. This Buffered Memory Model (BMM) targets the Java programming language. It is strictly less relaxed than the Java Memory Model. It is shown equivalent to an operational model but is restricted to TSO relaxations.

This paper extends the BMM in order to allows more reorderings. We present the new set of memory event reorderings rules that fully characterize the model and an alternative operational model that is again shown equivalent.

Tue 19 Jul
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13:50 - 15:20: Session 3FTfJP at Belli
Chair(s): Davide AnconaUniversity of Genova
13:50 - 14:20
Talk
FTfJP
Jonathan HoylandRoyal Holloway University of London, Matthew HagueRoyal Holloway University of London
14:20 - 14:50
Talk
FTfJP
14:50 - 15:20
Talk
FTfJP
Davide AnconaUniversity of Genova, Francesco Dagnino, Elena ZuccaUniversity of Genova